Sanitas EG - Papers

Company: Scientific Papers

2007

M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, G.R. Sechi, and R. Weigand, "Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform" accepted at the 22th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT07).

M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, L. Sterpone, and M. Violante, "Soft errors in SRAM-based FPGAs: a comparison of two complementary approaches" accepted at the 9th European Conference Radiation and Its Effects on Components and Systems (RADECS 2007).

2005

M. Alderighi, A. Candelori, F. Casini, S. D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, and G.R. Sechi, "SEU Sensitivity of Virtex Configuration Logic", accepted for publication in IEEE Trans. on Nuclear Science 2005.

M. Alderighi, A. Candelori, F. Casini, S. D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, and G.R. Sechi, "Heavy Ion Effects on Configuration Logic of Virtex FPGAs", in Proc. of at the 11th IEEE Int'l On-line Testing Symposium (IOLTS05), pp. 49-53.

2004

M. Alderighi, F. Casini, S. D'angelo, F. Faure, M. Mancini, S. Pastore, G.R. Sechi and R. Velazco,"Proposal for a Radiation Test of Virtex-Based Alus", in Proc. of the 7th European Conference on Radiation and its Effects on Components and Systems, Nordwijk, The Netherlands, pp. 341-345, Oct. 2004.

2003

M. Alderighi, F. Casini, S. D'Angelo, F. Faure, M. Mancini, S. Pastore, G.R. Sechi and R. Velazco,"Radiation test methodology for SRAM-based FPGAs by using THESIC+", Proc. of the 9th IEEE Int'l On-Line Testing Symposium, Kos, Greece, p. 162, Jul. 2003.

M. Alderighi, S. D'Angelo, M. Mancini and G.R. Sechi, "A Fault Injection Tool for SRAM-based FPGAs", Proc. of the 9th IEEE Int'l On-Line Testing Symposium, Kos, Greece, pp. 129-133, Jul. 2003.

M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, A. Marmo, S. Pastore and G.R. Sechi, "A Tool for Injecting SEU-like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs", Proc. of the 2003 IEEE Int'l Symposium on Defect and Fault-Tolerance in VLSI Systems, Cambridge (Massachussets), pp. 71-78, Nov. 2003.

2002

M. Alderighi, F. Casini, S. D'Angelo, D. Salvi and G.R. Sechi, "A Fault-Tolerance FPGA-based Multi-stage Interconnection Network for Space Applications", Proc. of the Int'l Workshop on Electronic Design, Test, and Applications, Christchurch, New Zealand, pp. 302-306, Jan. 2002.

2001

M. Alderighi, F. Casini, S. D'Angelo, D. Salvi and G.R. Sechi, "A Fault-Tolerance Scheme for a MIN-based Multi-Sensor System", Proc. of the 2001 IEEE Symposium on Field-programmable Custom Computing Machines, in press.

M. Alderighi, S. D'Angelo, C. Metra and G.R. Sechi, "Novel Fault-Tolerant Adder Design for FPGA-Based Systems", Proc. of the 7th IEEE Int'l On-Line Testing Workshop, Giardini Naxos-Taormina (Italy), pp. 54-58, JUl. 2001.

M. Alderighi, F. Casini, S. D'Angelo, D. Salvi and G.R. Sechi, "A Fault-Tolerance Strategy for a FPGA-based Multi-stage Interconnection Network in a Multisensor System for Space Applications", Proc. of the 2001 IEEE Int'l Symposium on Defect and Fault-Tolerance in VLSI Systems, San Francisco (California), pp. 191-199, Oct. 2001.

2000

M. Alderighi, S. D'Angelo, C. Metra and G.R. Sechi, "Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR non-Diverse ALUs", Proc. of the 2000 IEEE Int'l Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 155-163, Oct. 2000.

1999

C. Metra, S. D'Angelo and. Sechi, "Low performance Degradation Transient Fault Recovery for TMR Systems", Proc of the 5th IEEE Int'l On-Line Testing Workshop, Rhodes, Greece, p. 44-48, Jul. 1999.

M. Alderighi, S. D'Angelo, V. Piuri and G.R. Sechi, "Implementing A Self-Checking Neural System for Photon Event Identification by SRAM-based FPGAs", Proc. of the 1999 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Albuquerque (New Mexico), pp. 274-282, Nov. 1999.

S. D'Angelo, C. Metra and G.R. Sechi,"Transient and Permanent Fault Diagnosis for FPGA-based TMR Systems", Proc. of the 1999 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Albuquerque (New Mexico), pp. 330-338, Nov. 1999.

1998

M. Alderighi, F. Casini, R.P.G. Mazzei and G.R. Sechi, "Broadcast Automata: a Computational Model for Massively Parallel Symbolic Processing", Periodica Polytechnica Ser. Electrical Engineering 42, (1), 1998, pp. 49-70.

M. Alderighi, F. Casini and G.R. Sechi, "Typed Broadcast Automata for Modeling Massively Parallel Processing", Proc. of the Third Int'l Conference on Massively Parallel Computing Systems, Colorado Springs (Colorado), CD-ROM, The National Technological University Press, Apr. 1998.

M. Alderighi, F. Casini, R.P.G. Mazzei and G.R. Sechi, "Parallelism in Structured Program Execution", Proc. of the Third Int'l Conference on Massively Parallel Computing Systems, Colorado Springs (Colorado), CD-ROM, The National Technological University Press, Apr. 1998.

S. D'Angelo, C.Metra, S. Pastore, A. Pogutz and G.R. Sechi, "Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-based Systems", Proc. of the 1998 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Austin (Texas), pp. 233-240, Nov. 1998.


Home Company Mission Proposal Research Projects Courses Download		Company: Scientific Papers 2007 M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, G.R. Sechi, and R. Weigand, "Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform" accepted at the 22th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT07). M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, L. Sterpone, and M. Violante, "Soft errors in SRAM-based FPGAs: a comparison of two complementary approaches" accepted at the 9th European Conference Radiation and Its Effects on Components and Systems (RADECS 2007). 2005 M. Alderighi, A. Candelori, F. Casini, S. D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, and G.R. Sechi, "SEU Sensitivity of Virtex Configuration Logic", accepted for publication in IEEE Trans. on Nuclear Science 2005. M. Alderighi, A. Candelori, F. Casini, S. D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, and G.R. Sechi, "Heavy Ion Effects on Configuration Logic of Virtex FPGAs", in Proc. of at the 11th IEEE Int'l On-line Testing Symposium (IOLTS05), pp. 49-53. 2004 M. Alderighi, F. Casini, S. D'angelo, F. Faure, M. Mancini, S. Pastore, G.R. Sechi and R. Velazco,"Proposal for a Radiation Test of Virtex-Based Alus", in Proc. of the 7th European Conference on Radiation and its Effects on Components and Systems, Nordwijk, The Netherlands, pp. 341-345, Oct. 2004. 2003 M. Alderighi, F. Casini, S. D'Angelo, F. Faure, M. Mancini, S. Pastore, G.R. Sechi and R. Velazco,"Radiation test methodology for SRAM-based FPGAs by using THESIC+", Proc. of the 9th IEEE Int'l On-Line Testing Symposium, Kos, Greece, p. 162, Jul. 2003. M. Alderighi, S. D'Angelo, M. Mancini and G.R. Sechi, "A Fault Injection Tool for SRAM-based FPGAs", Proc. of the 9th IEEE Int'l On-Line Testing Symposium, Kos, Greece, pp. 129-133, Jul. 2003. M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, A. Marmo, S. Pastore and G.R. Sechi, "A Tool for Injecting SEU-like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs", Proc. of the 2003 IEEE Int'l Symposium on Defect and Fault-Tolerance in VLSI Systems, Cambridge (Massachussets), pp. 71-78, Nov. 2003. 2002 M. Alderighi, F. Casini, S. D'Angelo, D. Salvi and G.R. Sechi, "A Fault-Tolerance FPGA-based Multi-stage Interconnection Network for Space Applications", Proc. of the Int'l Workshop on Electronic Design, Test, and Applications, Christchurch, New Zealand, pp. 302-306, Jan. 2002. 2001 M. Alderighi, F. Casini, S. D'Angelo, D. Salvi and G.R. Sechi, "A Fault-Tolerance Scheme for a MIN-based Multi-Sensor System", Proc. of the 2001 IEEE Symposium on Field-programmable Custom Computing Machines, in press. M. Alderighi, S. D'Angelo, C. Metra and G.R. Sechi, "Novel Fault-Tolerant Adder Design for FPGA-Based Systems", Proc. of the 7th IEEE Int'l On-Line Testing Workshop, Giardini Naxos-Taormina (Italy), pp. 54-58, JUl. 2001. M. Alderighi, F. Casini, S. D'Angelo, D. Salvi and G.R. Sechi, "A Fault-Tolerance Strategy for a FPGA-based Multi-stage Interconnection Network in a Multisensor System for Space Applications", Proc. of the 2001 IEEE Int'l Symposium on Defect and Fault-Tolerance in VLSI Systems, San Francisco (California), pp. 191-199, Oct. 2001. 2000 M. Alderighi, S. D'Angelo, C. Metra and G.R. Sechi, "Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR non-Diverse ALUs", Proc. of the 2000 IEEE Int'l Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 155-163, Oct. 2000. 1999 C. Metra, S. D'Angelo and. Sechi, "Low performance Degradation Transient Fault Recovery for TMR Systems", Proc of the 5th IEEE Int'l On-Line Testing Workshop, Rhodes, Greece, p. 44-48, Jul. 1999. M. Alderighi, S. D'Angelo, V. Piuri and G.R. Sechi, "Implementing A Self-Checking Neural System for Photon Event Identification by SRAM-based FPGAs", Proc. of the 1999 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Albuquerque (New Mexico), pp. 274-282, Nov. 1999. S. D'Angelo, C. Metra and G.R. Sechi,"Transient and Permanent Fault Diagnosis for FPGA-based TMR Systems", Proc. of the 1999 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Albuquerque (New Mexico), pp. 330-338, Nov. 1999. 1998 M. Alderighi, F. Casini, R.P.G. Mazzei and G.R. Sechi, "Broadcast Automata: a Computational Model for Massively Parallel Symbolic Processing", Periodica Polytechnica Ser. Electrical Engineering 42, (1), 1998, pp. 49-70. M. Alderighi, F. Casini and G.R. Sechi, "Typed Broadcast Automata for Modeling Massively Parallel Processing", Proc. of the Third Int'l Conference on Massively Parallel Computing Systems, Colorado Springs (Colorado), CD-ROM, The National Technological University Press, Apr. 1998. M. Alderighi, F. Casini, R.P.G. Mazzei and G.R. Sechi, "Parallelism in Structured Program Execution", Proc. of the Third Int'l Conference on Massively Parallel Computing Systems, Colorado Springs (Colorado), CD-ROM, The National Technological University Press, Apr. 1998. S. D'Angelo, C.Metra, S. Pastore, A. Pogutz and G.R. Sechi, "Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-based Systems", Proc. of the 1998 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Austin (Texas), pp. 233-240, Nov. 1998.